Semiconductor tester synchronized with external clock

ABSTRACT

The present invention aims to take in an external clock signal generated by a device under test into a semiconductor tester and eliminate jitters involved in the clock signal, thereby stabilizes the clock signal, and to use the clock signal as an operation clock of the tester. Hence, a divider A11 which takes the clock signal 21 generated by the device under test as an input, a phase detector circuit 12, a loop filter 13, a VCO 14 and a divider B16 are provided. In addition, the invention includes a test rate generator 15 and an inter-leave circuit 18. The operation clock which is an output of the VCO 14 is input to the test rate generator 15 to output a test rate signal 23, and distributes the test rate signal to the inside circuits as well as feeds back to the phase detector 12 through the divider B16.

TECHNICAL FIELD

This invention relates to a synchronization circuit, to be used in asemiconductor tester to receive an external clock signal, which removesjitters of the clock signal and synchronizes an internal clock signal ofthe semiconductor tester with the external clock signal.

BACKGROUND ART

An example of the conventional technology is represented in FIG. 3. In asemiconductor tester, an operation clock signal is generated inside thetest system. Test patterns are generated in synchronism with the clocksignal and applied to a semiconductor device under test. The resultantoutput signals from the device under test are compared with expectedpattern. In such an arrangement, a problem of producing jitters does notoccur since all the operation in the system is synchronized with theinternal clock signal. On the other hand, there is a semiconductordevice which generates a clock signal by itself. In such a case, amethod may be used for utilizing the clock signal from the device itselfto operate the semiconductor tester. In this method, the internal clockof the semiconductor tester has to be synchronized with the clock signalfrom the device under test. However, the problem of jitters will occurbetween the two clocks as shown in FIG. 4 since the two clocks arecompletely out of synchronization.

Therefore, it is an object of the present invention to solve thisproblem and to provide a semiconductor tester circuit which will notgenerate jitters when using an external clock signal.

DISCLOSURE OF THE INVENTION

According to the first embodiment of this invention, a divider isprovided which receives an external clock signal generated by asemiconductor device under test at an input terminal and divides theclock signal by 1/N. A phase detector is provided which receives theoutput of the divider and an output of another divider. A loop filter isprovided which takes the output of phase detector as an input signal. Avoltage controlled oscillator (hereinafter "VCO") is provided whichreceives the output of the loop filter as an input. The output signal ofthe VCO is provided to an input of a test rate generator which providesthe output of the VCO to various circuits in the semiconductor tester. Adivider is provided which receives the output of the test rate generatoras an input signal and divides the input signal by 1/N. The output ofthe divider is taken as the input of the phase detector as noted above.

According to the second embodiment of the present invention, a testsignal frequency generator is provided which can set a test signalfrequency in high resolution, such as 1 Hz increment. A divider isprovided which receives a clock signal generated by the test signalfrequency generator at an input terminal and divides the received clocksignal by 1/N. A phase detector is provided which receives the output ofthe divider and an output of another divider. A loop filter is providedwhich takes the output of phase detector as an input signal. A VCO isprovided which receives the output of the loop filter as an input. Theoutput signal of the VCO is provided to an input of a test rategenerator which provides the output of the VCO to various circuits inthe semiconductor tester. A divider is provided which receives theoutput of the test rate generator as an input signal and divides theinput signal by 1/N. The output of the divider is taken as the input ofthe phase detector as noted above.

Because of the arrangement of the embodiments of the present inventiondescribed above, a phase Locked Loop (PLL) is formed by interactions ofthe divider A, the phase detector, the loop filter, the VCO and thedivider B. Thus, the clock signal received asynchronously can beconverted to an operation clock having high stability. In other words,the present invention provides an operation clock which does not havejitter components.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing the first embodiment of the presentinvention.

FIG. 2 is a block diagram showing the second embodiment of the presentinvention.

FIG. 3 is a block diagram showing the conventional technology.

FIGS. 4A-4B are diagrams for explaining jitters.

BEST MODE FOR CARRYING OUT THE INVENTION

A clock period of a clock signal 21 which is provided to an inputterminal 10 from a device 19 under test as shown in FIG. 1 is measuredin advance by a frequency counter. The measured value of the clockperiod is preset in a test rate generator 15. Only the differencebetween the first and second embodiments is whether a means ofgenerating the clock signal is a frequency generator 20 itself as shownin FIG. 2 or the clock signal generated by the device 19 under test asshown in FIG. 1. Hence the explanation hereafter applies to both cases.The clock signal 21 at the input of the divider A11 is also provided toan inter-leave circuit 18 as a clock signal to synchronize with inputsand outputs of the device 19 to be tested.

The frequency of the clock signal 21 which is input to the divider A11is designated by f which is asynchronous with an internal clock of thesemiconductor tester. The clock signal 21 provided to the divider A11 isdivided by 1/N. Hence, the output of the divider A11 is f1=f/N. A phasedetector 12 is provided which has two input terminals. One inputterminal of the phase detector 12 is provided with an input signal ofthe frequency f1, and the other input terminal is provided with an inputsignal having a frequency f2. The phase detector 12 outputs the phasedifferences between the frequencies f1 and f2. In a loop-filter 13, thisphase differences is taken as an input signal and is converted to acorresponding voltage signal. In a VCO 14, the converted voltage signalfrom the loop-filter 13 controls a frequency signal, and the resultedoutput signal is taken as an operation clock 23 for the semiconductortester.

The test rate generator 15 generates a test rate signal 22 by taking theoperation clock 23 as an input to use the test rate signal for theinternal circuits in the tester. The test rate signal is also input to adivider B16 where it is divided by 1/N to produce the frequency f2 whichis provide to another input terminal of the phase detector 12 as notedabove. In the foregoing arrangement, a PLL circuit is formed whichconverts the asynchronous clock signal 21 to the stabilized operationclock 23. The inter-leave circuit 18 performs the exchange of clocksignals between the test rate signal 22 and the clock signal 21, i.e.,from the test rate signal 22 to the clock signal 21 or from the clocksignal 21 to the test rate signal 22, to secure the signal transfer,such as applying test pattern signals to the device 19 under test orreceiving the resultant signal from the device 19 under test.

The inter-leave circuit 18 also makes it possible to provide a signalwhich has a resolution higher than a divided clock period.

The details of the inter-leave circuit which absorbs phase differencesis described in Japanese patent application No. 5-73506.

Since it is configured as described in the foregoing, the presentinvention has the following effects.

The present invention provides a circuit arrangement which will notproduce the jitters even when an external clock signal is used. Hencethe semiconductor tester can be operated by an actual operation clock ofthe device 19 under test. Further, in the present invention, the clocksignal of high frequency resolution can be used since it is possible toset the clock signal with a small frequency increment. Thus, the presentinvention has significant advantages over the conventional technology.

What is claimed is:
 1. A semiconductor tester synchronized with anexternal clock signal, comprising:A first divider (11) which receives anexternal clock signal (21) from a device (19) under test; a phasedetector (12) which is provided with the output signal of the firstdivider (11) and an output signal from a second divider (16), andgenerates a frequency difference between the two output signals; a loopfilter (13) which receives the output of the phase detector (12) as aninput and converts the frequency difference into a voltage signal; avoltage controlled oscillator (14) whose frequency is controlled by theoutput signal of the loop filter (13); a test rate generator (15) whichis provided with the output signal of the voltage controlled oscillator(14); said second divider (16) is provided with the output signal of thetest rate generator (15); an inter-leave circuit (18) which is providedwith the output signals of the test rate generator (15) and the clocksignal (21) as input clocks, and absorbs the phase differences betweenthe two.
 2. A semiconductor tester synchronized with an external clocksignal, comprising:a test frequency generator (20) which generates aclock signal; A first divider (11) which receives an external clocksignal (21) from the frequency generator (20); a phase detector (12)which is provided with the output signal of the first divider (11) andan output signal from a second divider (16), and generates a frequencydifference between the two output signals; a loop filter (13) whichreceives the output of the phase detector (12) as an input and convertsthe frequency difference into a voltage signal; a voltage controlledoscillator (14) whose frequency is controlled by the output signal ofthe loop filter (13); a test rate generator (15) which is provided withthe output signal of the voltage controlled oscillator (14); said seconddivider (16) is provided with the output signal of the test rategenerator (15); an inter-leave circuit (18) which is provided with theoutput signal of the test rate generator (15) and the clock signal (21)as input clocks, and absorbs the phase differences between the two.
 3. Asemiconductor tester synchronized with an external clock signal,comprising:A first divider (11) which receives an external clock signal(21); a phase detector (12) which is provided with the output signal ofthe first divider (11) and an output signal from a second divider (16),and generates a frequency difference between the two output signals; aloop filter (13) which receives the output of the phase detector (12) asan input and converts the frequency difference into a voltage signal; avoltage controlled oscillator (14) whose frequency is controlled by theoutput signal of the loop filter (13); a test rate generator (15) whichis provided with the output signal of the voltage controlled oscillator(14) as an input; said second divider (16) is provided with the outputsignal of the test rate generator (15) as an input; an inter-leavecircuit (18) which is provided with the output signals of the test rategenerator (15) and the clock signal (21) as input clocks, and absorbsthe phase differences between the two.